Mixed Signal
Power management, audio, battery management - from architecture to verification closure.
- IP & interface definition
- RTL implementation & lint / CDC
- UVM environments and coverage strategy
- Gate-level sims and closure support
The Engineering you can trust
great engineers.great projects.
We turn complex design constraints across Analog, mixed-signal designs, ASICs, FPGA prototypes, and AI compute platforms into precise, elegant, silicon-ready solutions.
2020
Founded in Graz
> 200
Years experience
100%
Central Europe team
At semify, we specialize in digital design and verification for advanced semiconductor development. Our experienced engineering team brings strong expertise in FPGA, ASIC, digital, and mixed-signal projects across power, AI, compute, and automotive applications. By working closely with our customers, we create tailored solutions that meet specific technical and business needs. With all engineers based in Central Europe, we ensure clear communication, close collaboration, and reliable execution throughout the project. semify delivers high-quality engineering support that helps customers move from concept to silicon with confidence.
Services
Discover our core expertises
Microcontroller Based
Motor control, battery charging, low-power CPU platforms - robust logic with clean interfaces.
- Subsystem design & integration
- Verification planning & regression
- Performance / power-focused reviews
- Lab-support oriented prototyping
AI / Compute
Energy-efficient NN acceleration with modern interconnect and memory subsystems.
- SoC / subsystem verification
- Clock / reset strategy support
- PCIe, DDR, Ethernet integration
- Verification quality gates
FPGA
High-speed measurement, waveform generation, platform bring-up - practical and test-first.
- Prototype architecture & build
- Reusable lab evaluation setups
- Open-source + commercial EDA mix
- Clear milestones and deliverables
How We Work
Flexible engagement, built around your needs
From embedded engineering support to independent, milestone-driven execution, we adapt our engagement model to match your project, team structure, and delivery goals.
Fully Integrated
- Integrated directly into your development team
- Flexible task ownership based on evolving priorities
- Support or leadership in architecture and specification
- Full design or block delivery within your existing flow
Delivery-Based
- Based on a clear and agreed specification
- Structured around defined milestones
- Focused on measurable deliverables
- Independent development with clear accountability
Process
From early architecture to post-silicon lab support
Milestone-based journey: START → DEFINE → BUILD → VERIFY → SIGNOFF → SUPPORT.
Capabilities
Frontend & backend design and verification
| Area | Typical work | Outputs |
|---|---|---|
| Architecture & spec | Requirements, interfaces, clocks / resets | Specs, interface docs, constraint intent |
| RTL implementation | SystemVerilog / Verilog, lint, CDC/RDC | RTL blocks, clean reports, reviews |
| Functional verification | UVM environments, assertions, coverage | Tests, regressions, coverage closure |
| Integration | IP bring-up, subsystems, quality gates | Integration plan, checkers, sign-off |
| FPGA prototyping | Prototypes, evaluation hooks, lab flows | Bitstreams, test harnesses, demos |
Hover a row to see what we bring to your project.
| Area | Typical work | Outputs |
|---|---|---|
| Synthesis & constraints | SDC intent, QoR strategy, reviews | Synth-ready RTL, constraints, QoR notes |
| DFT support | Scan readiness, MBIST/JTAG coordination | DFT checklists, clean handoff |
| Place & route | Floorplan support, CTS / routing guidance | Closure actions, risk tracking |
| STA & sign-off | STA reviews, corner strategy, sign-off prep | Reports, sign-off readiness status |
| GLS & ECO | Gate-level sims, ECO guidance | Validated fixes, closure support |
Hover a row to see how we support physical implementation and sign-off.
Projects
Reference projects
Mixed Signal ASIC - MEMS audio amplifier
Scope
From FPGA prototyping through to full digital logic implementation.
Key Skills
FPGA design, digital logic design and verification, PnR supervision, and a mixture of open-source, commercial and EDA tooling.
Added Value
Prototyping environment could be reused for lab evaluation. Successfully transitioned to open-source digital simulation, significantly reducing EDA licensing costs.
Collaboration with large OEMs
Scope
Mixed signal ASICs for power management and NFC applications.
Key Skills
Digital ASIC design, mixed-signal integration, and applying a customer-focused design methodology.
Added Value
Capability in handling high expectations and stringent quality demands of premium global customers.
Server / AI chip - SoC verification
Scope
Top-level SoC verification, subsystem verification, and gate-level simulations.
Key Skills
Dynamic clock domain crossing (CDC), functional verification, gate-level simulation, and flexible verification strategies.
Added Value
Enhanced flexibility and accuracy of verification through dynamic CDC improvements, ensuring robust design validation.
Open source RISC-V core
Scope
Integrate and customize open-source RISC-V cores such as CVA6 and Ibex into SoC environments, including interconnects, memory systems, and peripherals. Develop end-to-end verification, software bring-up, FPGA prototyping, and pre-silicon validation.
Key Skills
RISC-V architecture knowledge, RTL design, AXI/AHB/APB SoC integration, UVM verification, assertions, coverage-driven methods, and waveform debug.
Added Value
Experience integrating and verifying open-source RISC-V cores including CVA4/CVA6, lowRISC Ibex, and Google Coral core across full SoC environments.
Edge AI-based application
Scope
Design and deploy optimized AI/ML models for edge devices with focus on low latency, power efficiency, and real-time inference. Integrate AI pipelines with embedded systems and hardware accelerators such as Google Coral Edge TPU.
Key Skills
TensorFlow Lite, PyTorch Mobile, quantization, pruning, embedded C/C++ and Python, Linux/RTOS systems, and edge hardware experience.
Added Value
Experience with Edge AI applications, deploying and optimizing AI inference pipelines on resource-constrained edge hardware.
Mixed Signal ASIC - MEMS audio amplifier
Reuse prototyping environment for lab evaluation.
Collaboration with large OEMs
Customer-focused methodology with stringent quality demands.
Server / AI chip - SoC verification
Dynamic CDC improvements for robust design validation.
Open source RISC-V core
Performance acceleration using custom instruction core.
Edge AI-based application
Optimizing AI inference pipelines on resource-constrained edge hardware.
About
We are semify
semify is an independent engineering team based in Graz, Austria, focused on delivering silicon-ready digital design solutions for mixed-signal ASICs.
Established in 2020 by DI Klaus Strohmayer, semify was built with a clear mission: to help customers turn complex requirements into reliable, high-quality digital implementations. Our expertise covers a broad range of architectures, from microcontroller-based systems to dedicated state-machine designs.
We support the complete development journey, from early concept and prototyping through design, verification, and evaluation. With additional strength in FPGA development, we provide flexible engineering support tailored to each project and aligned with real delivery goals.
Careers
A company based on balance
We love great engineering - and we care about sustainable ways of working. If you share our spirit, let's talk.
At semify, we continually look for talented and skilled individuals to work on exciting projects. Our dynamic work environment offers numerous opportunities for both technical and social skill development. As a business founded by a family-oriented professional, we deeply value the importance of balancing career and personal life. Our flexible core hours are designed to support this balance, while our focus remains firmly on delivering meaningful results. We believe that individual well-being and a strong sense of community are just as essential as professional achievement.
Open positions
Lifelong learning isn’t just a phrase for you - it’s your mindset?
Then join us in our modern, fully equipped office in Graz and Budapest and experience the multicultural, vibrant life of Austria’s second-largest city and Hungary’s dynamic capital. We’re waiting for you to shape the future together - apply now by sending us your CV, including your project experience, for the following position(s). We encourage you to include a short cover letter as well, giving us insight into your current situation and future aspirations.
We review every application carefully and respond to all candidates.
Digital Verification Engineer
Digital Design Engineer ASIC/FPGA
Benefits
Benefits
Contact
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