Mixed Signal Designs
Flow State
Skills
Tooling
Synthesis
Synthesis Scan Insertion (DfT) STA
Genus, Design Compiler Vivado Tempus
Physical Implementation
PnR supervision STA, LEC
Genus Design Compiler Vivado
AMS Verification
AMS Simulation (RTL, GLS) Analog modelling
Simvision
Gatelevel Verification
GLS Simulation Power Simulation C-based test cases
Simvision, Questa PrimePower gcc, clang
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